1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various methods that involve color-aware retargeting of individual decomposed patterns when designing masks or reticles to be used in multiple patterning processes, such as double patterning processes, and the use of such masks or reticles in various photolithography systems to manufacture integrated circuit products.
2. Description of the Related Art
Photolithography is one of the basic processes used in manufacturing integrated circuit products. At a very high level, photolithography involves (1) forming a layer of light or radiation-sensitive material, such as photoresist, above a layer of material or a substrate, (2) selectively exposing the radiation-sensitive material to a light generated by a light source (such as a DUV or EUV source) to transfer a pattern defined by a mask or reticle (inter-changeable terms) to the radiation-sensitive material, and (3) developing the exposed layer of radiation-sensitive material to define a patterned mask layer. Various process operations, such as etching or ion implantation processes, may then be performed on the underlying layer of material or substrate through the patterned mask layer.
The design and manufacture of reticles used in such photolithography processes is a very complex and expensive undertaking as such masks must be very precise and must enable the repeated and accurate formation of a desired pattern in the underlying layer of material (for an etching process). It is well known that, for a variety of reasons, photolithography systems do not print features in a layer of photoresist that correspond exactly to the features depicted in a theoretical target exposure pattern, e.g., the lengths of line-type features may be shorter than anticipated, corners may be rounded instead of square, etc. There are several factors that cause such printing differences, such as interference between light beams transmitted through adjacent patterns, resist processes, the reflection of light from adjacent or underlying materials or structures, unacceptable variations in topography, etc. One technique used in designing and developing masks for use in semiconductor manufacturing to overcome or at least reduce such optical proximity errors involves the use of software-based optical proximity correction (OPC) techniques in an effort to make sure that a mask, when used, generates the desired pattern on the target material or structure in a reliable and repeatable manner.
In recent years, the accuracy of pattern transfer in photolithography processes has become even more important and more difficult due to, among other things, the ongoing shrinkage of various features on integrated circuit devices. Of course, the ultimate goal in integrated circuit fabrication is to faithfully reproduce the original circuit design on the integrated circuit product. Historically, the feature sizes and pitches (where the pitch is equal to the width of the feature plus the spacing between identical edge features) employed in integrated circuit products were such that a desired pattern could be formed using a single patterned photoresist masking layer. However, in recent years, device dimensions and pitches have been reduced to the point where existing photolithography tools, e.g., 193 nm wavelength photolithography tools, cannot perform a single exposure process to form a single patterned mask layer that will enable the formation of all of the desired features of the overall target pattern.
Accordingly, lithography engineers have resorted to various resolution enhancement techniques to form features on integrated circuit products. Such resolution enhancement techniques include, but are not limited to, so-called multiple-exposure (e.g., “double exposure”) and multiple-patterning (e.g., “double patterning” or “triple patterning”) techniques. It is understood that these general categories can be extended beyond two masks to include multiple exposures and multiple patterning; however, in the present application, only double exposure and double patterning will be referenced. In some double exposure processes, a single layer of photoresist material is subjected to two different exposures using two different reticles, and that single, twice-exposed layer of photoresist is then developed and processed to create the final patterned photoresist masking layer that will be used in performing a process operation, e.g., an etching process, to define features or structures of an integrated circuit product. Other variations in such a double exposure process are known to those skilled in the art. In a double patterning process, an intermediate transfer mask layer is formed above a layer that is to be patterned, e.g., a layer of gate electrode material. Thereafter, a first photoresist layer is exposed with a first mask, then developed, and the pattern in the first patterned photoresist mask layer is transferred to the underlying intermediate transfer mask layer by performing an etching process through the first patterned photoresist mask layer. Then, the first patterned photoresist mask layer is removed and a second layer of photoresist material is formed above the partially patterned intermediate transfer mask layer. The second photoresist layer is then exposed with a second mask, and then developed, and the pattern in the second patterned photoresist mask layer is transferred to the underlying intermediate transfer mask layer by performing an etching process through the second patterned photoresist mask layer. This results in the intermediate transfer mask layer having the pattern reflected by the combination of the first and second patterned photoresist mask layers. The second patterned photoresist mask is then removed, and the underlying layer to be patterned is thereafter patterned using the now fully patterned intermediate transfer mask layer. While such techniques effectively increase the complexity of the photolithography process, they do result in improving the achievable resolution and they enable the printing of far smaller features that would otherwise not be possible using existing photolithography tools and a single masking layer, single exposure, lithography process. There are many variations of double exposure and double patterning process operations and, as will be appreciated by one skilled in the art after a complete reading of the present application, many of those variations may benefit from the methodologies set forth in the present application. For clarity, in the subsequent discussion, no distinction will be made between double exposure and double patterning process operations, and, in all cases, these will simply be referred to as double patterning processes.
Despite all of these techniques, the lithography process that is exerted to a point at or near its limits will still not allow all patterns to be faithfully reproduced on the wafer in the presence of normal manufacturing process variations. As a result, some design target shapes must be modified to align with process capabilities. Such a so-called “retargeting” process often involves making isolated patterns larger, making patterns with small areas larger and/or smaller and expanding regions where patterns transition from one periodicity to another (i.e., so-called fan-out regions). In general, retargeting is done in an effort to make manufacturing easier and to get more process margins in regions where features sizes can be changed.
The photolithographic masks or reticles referred to above comprise geometric patterns corresponding to the circuit components that are part of an integrated circuit product. The patterns used to create such masks or reticles are generated utilizing computer-aided design (CAD) programs, wherein this process is sometimes referred to as electronic design automation. Most CAD programs follow a set of predetermined design rules in order to create functional masks. These rules are set by processing and design limitations. For example, design rules define the space tolerance between circuit devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the circuit devices or lines do not interact with one another in an undesirable way. The design rule limitations are typically referred to as “critical dimensions” (CD). A critical dimension of a circuit can be defined as the smallest width of a line or hole or the smallest space between two lines or two holes. Thus, the CD determines the overall size and density of the designed circuit.
FIGS. 1A-1E and FIG. 2 (flowchart form) depict one illustrative example of a prior art method of retargeting an overall target exposure pattern that is to be formed using double patterning processes. As shown in FIG. 1A, an initial overall target exposure pattern 10 is comprised of a plurality of features 12. For ease of reference, the features 12 have been labeled with additional numerical reference numbers 1-4. In the particular example depicted in FIG. 1A, the features 12 all have the same critical dimension (width), but the spacing between the features 2-3 is less than the spacing between the features 1-2 and 3-4. The space (or pitch) between the features 12 in the initial overall target pattern 10 is such that the initial overall target pattern 10 cannot be printed using a single mask with available photolithography tools. Thus, as shown in FIG. 1B and step 22 of FIG. 2, the initial overall target exposure pattern 10 is decomposed into a first exposure pattern 10A (comprised of the features 1 and 3) and a second exposure pattern 10B (comprised of the features 2 and 4). Shading has been added to the features 12 in the second exposure mask 10B for ease of explanation. At the point depicted in FIG. 1B, the decomposed first exposure pattern 10A and second exposure pattern 10B will be subject to various design rule checks (DRC) to make sure that the decomposed first and second exposure patterns 10A, 10B can each be patterned using a single layer of photoresist material without exceeding the capability of the photolithography tools and systems that will be used to manufacture an integrated circuit product.
As shown in FIG. 1C and step 24 of FIG. 2, after the first and second exposure patterns 10A, 10B have passed the various design rule checks, the first and second exposure patterns 10A, 10B will be recombined into a recombined overall target exposure pattern 10R.
With reference to FIG. 1D and step 26 of FIG. 2, the next process operation involves retargeting of the recombined overall target exposure pattern 10R. More specifically, using the recombined overall target exposure pattern 10R as the starting point, the width of the feature 1 in the first exposure pattern 10A is increased by an amount indicated by the arrow 14, while the width of the feature 4 in the second exposure pattern 10B is increased by an amount indicated by the arrow 16. As shown in FIG. 1D, this retargeting results in a retargeted, recombined overall pattern 10RT comprised of the original features 2, 3 and the retargeted (enlarged) features 1 and 4. As discussed above, such changes in the width of the features 1 and 4 may facilitate more accurate manufacturing. Of course, the changes in the width of the features 1 and 4 need not be the same.
Thereafter, as indicated in FIG. 1E and step 28 of FIG. 2, the retargeted, recombined overall target exposure pattern 10RT is decomposed into the first and second exposure patterns 10A, 10B. Then, as indicated at decision block 30 in FIG. 2, the decomposed first and second exposure patterns 10A, 10B are examined to determine if they are design rule compliant. If the decomposed first and second exposure patterns 10A, 10B are not design rule compliant (the “NO” branch), then the process restarts at step 22 in FIG. 2. Various changes may be made to any or all of the first and second exposure patterns 10A, 10B, as well as the overall target exposure pattern 10, until such time as the first and second exposure patterns 10A, 10B can pass the design rule check indicated at decision block 30 in FIG. 2.
Ultimately, when the mask design process is completed, data corresponding to the first and second exposure patterns 10A, 10B (modified as necessary during the design process) will be provided to a mask manufacturer that will produce a tangible mask (not shown) to be used in a photolithographic tool to manufacture integrated circuit products. More specifically, the various sub-wavelength resolution assist features (SRAF) may be added to one or both of the first and second exposure patterns 10A, 10B, optical proximity correction (OPC) and/or OPC verification analysis (OPCVA) may thereafter be performed on the first and second exposure patterns 10A, 10B, as indicated in blocks 32 and 36. The data corresponding to the first and second exposure patterns 10A, 10B may then be provided to the mask manufacturer, as indicated in blocks 34 and 38.
The present disclosure is directed to various methods that involve color-aware retargeting of individual decomposed patterns when designing masks or reticles to be used in multiple patterning processes, such as double patterning processes, and the use of such masks or reticles in various photolithography systems to manufacture integrated circuit products.